For more than five decades, Moore’s Law has governed the pace of innovation in the semiconductor industry – driving evolution in the computing space from the early desktops and laptops to cloud computing and Internet of Things today.
Every 18 to 24 months, double the number of transistors per unit area were crammed into our silicon chips. This helped reduce cost as well as improve performance and power consumption in successive generations of microchips. As microchips became more compact, it also helped pave the way for thinner compute form factors including the mobile phones, tablets and ultrathin laptops.
Moore’s Law is slowing, and it is more challenging than ever before to deliver improvements every 18-24 months. Shrinking dimensions is significantly challenging and it’s taking longer to discover new manufacturing technologies that allow continued miniaturization of silicon.
From an industry standpoint, this stagnation really puts a premium on innovation. The processor design approach must make up for the gaps, to deliver product-level improvements at the pace of traditional Moore’s Law.
The Chiplet Approach
We need a new processor design approach to extend the historical gains seen over the past few decades into the decades to come. One established solution is the chiplet approach, where you build a single processor package using several different chiplets and connect them using a die-to-die interconnect scheme. Chiplets make it faster and cheaper to flexibly assemble I/O, memory and processor cores. Many industry players are moving towards this modular design approach.
If the design approach anticipates modular architecture, then portions of the design that are difficult to manufacture can be parsed into small die sizes. With small die, we get increased yield and increased number of chips per wafer, which will help further reduce manufacturing costs and increase production efficiency.
There are several important factors that make a chiplet architecture compelling:
- The product needs to have a huge appetite for throughput performance such that the cost of multiple smaller die in the package are significantly lower than legacy monolithic designs,
- There needs to be a substantial component of analog / mixed signal IP that does not benefit from leading edge technology,
- The product should benefit from the flexibility enabled by varying the chiplet count across the product line. For instance, at AMD, we sell one, two and four die versions of our “Zen” architecture in AMD Ryzen™, Ryzen™ Threadripper™ and EPYC processors.
The 7nm Leap
7nm is an important step in the chiplet strategy. Small 7nm CPU chiplets are not only efficient and cost effective, they enable unprecedented cost and power configurability of the product by populating varying numbers of them based on market segment requirements.
The other obvious benefit is that by combining all the memory and I/O interfaces onto a monolithic I/O die, companies can help improve performance by reducing average latencies for memory and IO. In computing systems like Servers, where power and performance are completely dominated by the CPU cores and caches, getting the 7nm benefits for that IP is the key.
The resultant benefits to the end user include enhanced performance, lower power consumption, improved memory latency as well as clock speed.
The chiplet approach is the new direction for the semiconductor industry. The advances in performance, efficiency and architectural flexibility based on this modular strategy will extend Moore’s Law benefits in the future.
Further, the use of the chiplet approach will enable new innovations for the semiconductor industry to meet the demand for ever-increasing processing performance and specialized computing tasks in areas such as AI, real-time graphics rendering and simulations, and supercomputing.
Mark Papermaster is the CTO and Executive Vice President at AMD.